1. Field of the Invention
The present invention relates in general to a method for verifying optimization of processor link. In particular, the present invention relates to a method for verifying optimization of processor link by detecting a signal voltage level output from a Southbridge.
2. Description of the Related Art
Legacy I/O bus architectures are widely used in embedded systems because they are low cost and easily implemented using established software and hardware standards. These busses, however, top out at 66 MHz or so. Recently, processors operating at 500 MHz and 1 GHz and up clock frequencies need a faster alternative to these low bandwidth busses.
Lightning data transport (LDT) I/O bus, sometimes referred to hyper-transport (HT) I/O bus, delivers the high bus width needed for high performance applications in networking, communications and other embedded applications in a flexible, extensible and easily implemented bus structure. A scalable solution, the LDT I/O bus is capable of providing bus width for next generation processors and communications systems. A multivendor standard that is easily implemented, the LDT solution provides a broad selection of bus widths and speeds meeting the power, space and cost requirements of a wide range of embedded systems from low cost desktop workstations to digital consumer applications, communication systems, and networking equipment.
The optimization of LDT I/O bus is achieved through disconnection and reconnection of the LDT I/O bus enabling the LDT I/O bus to perform at desired bus width and operating frequency.
FIG. 1 is a schematic diagram of a conventional computer system comprising an LDT bus. As shown in the figure, LDT bus 12 is connected between CPU 10 and the Northbridge 14. Here, CPU 10 is an AMD K8 CPU, although the invention encompasses a wide range of CPU types, makes and models. Another bus 16 is connected between the Northbridge 14 and the Southbridge 18. LDT bus 12 connected between CPU 10 and the Northbridge 14 is disconnected and reconnected during power management of CPU and LDT bus optimization. The disconnection and reconnection of LDT bus 12 are performed according to the voltage level of the signal LDTSTOP# output by the Southbridge 18. The Southbridge 18 asserts the signal LDTSTOP# and outputs the asserted signal LDTSTOP#. The asserting of the signal LDTSTOP# transforms the voltage level of the signal LDTSTOP# from a normal level (high level as an example) to a low level.
LDT bus 12 is disconnected when both CPU 10 and the Northbridge 14 receive the asserted signal LDTSTOP#. Next, the timer 19 of the Southbridge 18 begins to calculate an elapsed time value. The Southbridge 18 de-asserts the signal LDTSTOP# when the elapsed time value of the timer 19 reaches a predetermined value. The de-asserting of the signal LDTSTOP# transforms the voltage level of the signal LDTSTOP# from the low level to the high level. LDT bus 12 is reconnected when both CPU 10 and the Northbridge 14 receive the de-asserted signal LDTSTOP#. Thus, LDT bus operates at another operating frequency and bus width.
FIG. 2 is a flowchart of the optimization of bus width and operating frequency of a conventional LDT I/O bus. First, LDT bus is initialized by basic input/output system (BIOS) (S1), such as by setting the optimized bus width and operating frequency of LDT bus connected between CPU and the Northbridge after booting. For example, the bus width of the LDT bus may be initialized as 8-bit, but can be changed to 16-bit after optimization. The operating frequency of the LDT bus may be initialized as 200 MHz, but can be changed to 400 MHz, 600 MHz or 800 MHz after optimization. Here, the optimized bus width and operating frequency of LDT bus is set by BIOS. Next, power management registers of CPU and the chipset comprising a Northbridge and a Southbridge are initialized by BIOS to set the related power setting (S2). Next, an auto-resume timer in the Southbridge is initialized for calculating an elapsed time value (S3). Next, BIOS issues a read request to a Southbridge power management I/O (PMIO) offset 15h for asserting a signal LDTSTOP# (S4). Here, assertion of the signal LDTSTOP# transforms a high level signal LDTSTOP# to a low level signal LDTSTOP#. The LDT bus connected between CPU and the Northbridge is disconnected when the signal LDTSTOP# is asserted (S5).
Next, the Southbridge de-asserts the signal LDTSTOP# when the elapsed time value of the timer initialized in step S3 reaches a predetermined value (S6). Here, de-assertion of the signal LDTSTOP# transforms a low level signal LDTSTOP# to a high level signal LDTSTOP#. Thus, the LDT bus connected between CPU and the Northbridge is reconnected when the signal LDTSTOP# is de-asserted (S7). Therefore, the LDT bus operates at optimized bus width and operating frequency set in BIOS. Thus, optimization of bus width and operating frequency of LDT bus is completed.
The conventional LDT bus optimization described must disconnect and reconnect the LDT bus to change the bus width and operating frequency thereof. However, the bus width and operating frequency of LDT bus are not changed when the disconnection and reconnection processes of the LDT bus perform unsuccessfully. Thus, the bus optimization fails and performance is poor.
However, the disconnection and reconnection processes of the LDT bus may never occur due to an inaccurate register setting by system BIOS. It is thus difficult to detect completion of the asserted and de-asserted signal LDTSTOP# sequences. It is inconvenient to debug the system if the signal LDTSTOP# pin must be probed by oscilloscope every time. Moreover, even when asserted and de-asserted signals LDTSTOP# are detected, broken circuits at the connection between the Southbridge 18 and CPU 10 or the Northbridge 14 can cause bus optimization to failed.